Copper-elastomer hybrid thermal interface material to cool under-substrate silicon

ABSTRACT

In some embodiments, copper-elastomer hybrid thermal interface material to cool under-substrate silicon is presented. In this regard, an apparatus is introduced having a layer of copper, a layer of elastomer, and a layer of thin film thermal interface material between the copper and elastomer layers. Other embodiments are also disclosed and claimed.

FIELD OF THE INVENTION

Embodiments of the present invention generally relate to the field of integrated circuit package cooling methods and, more particularly, to copper-elastomer hybrid thermal interface material to cool under-substrate silicon.

BACKGROUND OF THE INVENTION

The demand for small form-factor, high-speed computing devices has led to placing silicon components such as voltage regulators on the substrate of an integrated circuit package. A voltage regulator can produce a significant amount of heat that could impact the performance and reliability of the integrated circuit package.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:

FIG. 1 is a graphical illustration of a cross-sectional view of an integrated circuit package with under-substrate silicon;

FIG. 2 is a graphical illustration of a cross-sectional view of copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention;

FIG. 3 is a graphical illustration of a cross-sectional view of an integrated circuit package with copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention; and

FIG. 4 is a block diagram of an example electronic appliance suitable for implementing copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention.

DETAILED DESCRIPTION

In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that embodiments of the invention can be practiced without these specific details. In other instances, structures and devices are shown in block diagram form in order to avoid obscuring the invention.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 1 is a graphical illustration of a cross-sectional view of an integrated circuit package with under-substrate silicon. As shown, integrated circuit package 100 includes one or more of substrate 102, processor 104, contacts 106, heat spreader 108, under-substrate silicon 110, contacts 112, socket 114, printed circuit board 116, and air gap 118.

Substrate 102 provides mechanical support and signal routing for processor 104. In one embodiment substrate 102 is a multi-layer organic substrate. In another embodiment, substrate 102 is a ceramic substrate.

Processor 104 represents an integrated circuit device, for example a multi-core microprocessor which is connected to substrate 102 by contacts 106, which may be solder balls. Heat spreader 108 is designed to dissipate heat generated by processor 104.

Under-substrate silicon 110 may represent a voltage regulator that provides power for processor 104 and is connected to substrate 102 by contacts 112.

Socket 114 represents a material such as plastic that provides mechanical support and attachment for an integrated circuit package and includes contacts to electrically couple integrated circuit package 100 with traces and other components (not shown) on printed circuit board 116. In one embodiment, socket 114 is a land grid array (LGA) socket with contacts arranged in a square pattern around a central cavity. Printed circuit board 116 may represent a motherboard that is integrated into an electronic appliance.

Air gap 118 represents the space below under-substrate 110 and above printed circuit board 116. Additionally, there would be no air flowing to air gap 118, because it is surrounded by socket 114.

FIG. 2 is a graphical illustration of copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention. In accordance with one example embodiment, thermal interface material 200 includes one or more of copper layer 202, elastomer layer 204, and thin film layers 206.

Thermal interface material is designed to fit in air gap 118 and dissipate heat from under-substrate silicon 110. While shown as including one copper layer and one elastomer layer to minimize the number of material interfaces, thermal interface material 200 may include any number of copper and elastomer layers. In one embodiment, thermal interface material 200 has a length and width slightly larger than that of under-substrate silicon 110. In one embodiment, thermal interface material 200 is about 10 mm by 15 mm.

Copper layer 202 represents the primary thermal conductor of thermal interface material 200. However, copper is not easily compressed, and to maintain contact between under-substrate silicon 110 and printed circuit board 116 for a range of air gaps, elastomer layer 204 is included.

Elastomer layer 204 may be designed for compressibility and thermal conductivity. In one embodiment, elastomer layer 204 has a bulk thermal conductivity of about 3 W/m C. In one embodiment, where the nominal air gap 118 is 3 mm, copper layer 202 is 2 mm thick and elastomer layer 204 is 2 mm thick when uncompressed and 1 mm thick when compressed.

Thin film layers 206 is applied to the material interface surfaces of thermal interface material 200 to increase effective contact area and reduce thermal contact resistances. Thin film layers may consist primarily of thermal grease, solder alloy, phase change material, such as Honeywell PCM45T, or any combination of the above.

FIG. 3 is a graphical illustration of a cross-sectional view of an integrated circuit package with copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention. As shown, integrated circuit package 100 includes thermal interface material 200 between under-substrate silicon 110 and printed circuit board 116. The surface of printed circuit board 116 that contacts thermal interface material 200 may be fiberglass or a metal pad capable of further dissipating heat. In one embodiment, thermal interface material 200 is preformed and hand placed on printed circuit board 116 before integrated circuit package 100 is placed in socket 114.

FIG. 4 is a block diagram of an example electronic appliance suitable for implementing copper-elastomer hybrid thermal interface material to cool under-substrate silicon, in accordance with one example embodiment of the invention. Electronic appliance 400 is intended to represent any of a wide variety of traditional and non-traditional electronic appliances, laptops, desktops, cell phones, wireless communication subscriber units, wireless communication telephony infrastructure elements, personal digital assistants, set-top boxes, or any electric appliance that would benefit from the teachings of the present invention. In accordance with the illustrated example embodiment, electronic appliance 400 may include one or more of processor(s) 402, memory controller 404, system memory 406, input/output controller 408, network controller 410, and input/output device(s) 412 coupled as shown in FIG. 4. Processor(s) 402, or other integrated circuit components of electronic appliance 400, may include under-substrate silicon coupled with a thermal interface material described previously as an embodiment of the present invention.

Processor(s) 402 may represent any of a wide variety of control logic including, but not limited to one or more of a microprocessor, a programmable logic device (PLD), programmable logic array (PLA), application specific integrated circuit (ASIC), a microcontroller, and the like, although the present invention is not limited in this respect. In one embodiment, processors(s) 402 are Intel® compatible processors. Processor(s) 402 may have an instruction set containing a plurality of machine level instructions that may be invoked, for example by an application or operating system.

Memory controller 404 may represent any type of chipset or control logic that interfaces system memory 406 with the other components of electronic appliance 400. In one embodiment, the connection between processor(s) 402 and memory controller 404 may be referred to as a front-side bus. In another embodiment, memory controller 404 may be referred to as a north bridge.

System memory 406 may represent any type of memory device(s) used to store data and instructions that may have been or will be used by processor(s) 402. Typically, though the invention is not limited in this respect, system memory 406 will consist of dynamic random access memory (DRAM). In one embodiment, system memory 406 may consist of Rambus DRAM (RDRAM). In another embodiment, system memory 406 may consist of double data rate synchronous DRAM (DDRSDRAM).

Input/output (I/O) controller 408 may represent any type of chipset or control logic that interfaces I/O device(s) 412 with the other components of electronic appliance 400. In one embodiment, I/O controller 408 may be referred to as a south bridge. In another embodiment, I/O controller 408 may comply with the Peripheral Component Interconnect (PCI) Express™ Base Specification, Revision 1.0a, PCI Special Interest Group, released Apr. 15, 2003.

Network controller 410 may represent any type of device that allows electronic appliance 400 to communicate with other electronic appliances or devices. In one embodiment, network controller 410 may comply with a The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 802.11b standard (approved Sep. 16, 1999, supplement to ANSI/IEEE Std 802.11, 1999 Edition). In another embodiment, network controller 410 may be an Ethernet network interface card.

Input/output (I/O) device(s) 412 may represent any type of device, peripheral or component that provides input to or processes output from electronic appliance 400.

In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

Many of the methods are described in their most basic form but operations can be added to or deleted from any of the methods and information can be added or subtracted from any of the described messages without departing from the basic scope of the present invention. Any number of variations of the inventive concept is anticipated within the scope and spirit of the present invention. In this regard, the particular illustrated example embodiments are not provided to limit the invention but merely to illustrate it. Thus, the scope of the present invention is not to be determined by the specific examples provided above but only by the plain language of the following claims. 

1. An apparatus comprising: a layer of copper; a layer of elastomer; and a layer of thin film thermal interface material between the copper and elastomer layers.
 2. The apparatus of claim 1, wherein the thin film thermal interface material comprises a principal material chosen from the group consisting of: thermal grease, phase-change material, and solder alloy.
 3. The apparatus of claim 2, further comprising layers of thin film thermal interface material on outside mating surfaces of the copper and elastomer layers.
 4. The apparatus of claim 3, wherein the elastomer layer has a bulk thermal conductivity of about 3 W/m C.
 5. The apparatus of claim 3, further comprising an elastomer layer height of about 2 mm uncompressed.
 6. The apparatus of claim 4, wherein the elastomer layer height is designed to be about 1 mm compressed.
 7. The apparatus of claim 3, wherein the copper layer has a thickness of about 2 mm.
 8. The apparatus of claim 3, further comprising a length of about 15 mm.
 9. The apparatus of claim 3, further comprising a width of about 10 mm.
 10. An electronic appliance comprising: a network controller; a system memory; a processor, wherein the processor includes an under-substrate silicon die; and a thermal interface material coupled with the under-substrate silicon die, the thermal interface material comprising a layer of copper, a layer of elastomer, and a layer of thin film thermal interface material between the copper and elastomer layers.
 11. The electronic appliance of claim 10, further comprising layers of thin film thermal interface material on outside mating surfaces of the copper and elastomer layers.
 12. The electronic appliance of claim 11, wherein the thin film thermal interface material comprises a principal material chosen from the group consisting of: thermal grease, phase-change material, and solder alloy.
 13. The electronic appliance of claim 12, wherein the elastomer layer has a bulk thermal conductivity of about 3 W/m C.
 14. The electronic appliance of claim 12, further comprising a thermal interface material height of about 4 mm uncompressed.
 15. The electronic appliance of claim 14, wherein the thermal interface material height is designed to be about 3 mm when compressed. 